1. Field of the Invention
The present invention generally relates to analog integrated circuit layout, and more particularly to a nonlinear optimization method for resistor matching in analog integrated circuits.
2. Description of Related Art
Integrated circuit (IC) layout is a representation of an integrated circuit in terms of planar geometric shapes corresponding to layer patterns of the integrated circuit. The key performance of modern analog integrated circuits, such as digital-to-analog converters (DACs), is related to the accuracy of resistance ratios. Severe distortion will present between the input and output signals if the resistors in the analog ICs are mismatched. Due to the cost issue, designers usually design an IC under the strict fixed-outline constrains. To fit the whole design into the fixed-sized chip, devices with low shape flexibility, such as macros and IPs, are placed first. After that, resistors with high shape flexibility are placed in the remaining space. However, the remaining space for resistors is usually in rectilinear shape rather than rectangular shape, and the resistors placement thus becomes a challenge of layout engineers. FIG. 1A shows a layout with a resistor block A according to a conventional method. FIG. 1B shows an enlarged view of the resistor block that is composed of three local matching resistor blocks with their associated centroids, and therefore the resistor block A as a whole commonly does not have high matching quality.
Although several works have studied the detail about the matching methodologies, however, none of the existing works has proposed a methodology to consider matching quality and fixed-outline constraint simultaneously.
Accordingly, a need has thus arisen to propose a novel method of resistor matching in analog integrated circuit layout to effectively improve matching quality and conform to fixed-outline constraint.